The embodiments of the invention generally relate to integrated circuit structures and, more specifically, to an integrated circuit structure, a design structure for the integrated circuit structure and a method of forming the integrated circuit structure with improved isolation and, in the case of a radio frequency (RF) device (e.g., a RF switch) with reduced harmonics.
Integrated circuit devices formed in or above the active semiconductor layer (e.g., the active silicon layer) of a semiconductor-on-insulator (SOI) wafer often suffer from performance degradation due to coupling capacitance between the integrated circuit devices and the wafer substrate (e.g., a silicon substrate). Some integrated circuit devices, such as radio frequency (RF) switches, further suffer due to harmonics resulting from the resulting charge layer at the interface between the SOI insulator layer (e.g., the buried oxide (BOX) layer) and the wafer substrate. Therefore, there is a need in the art for a semiconductor structure that is formed using an SOI wafer and that has reduced harmonics and improved isolation between the active semiconductor layer and the wafer substrate.